The present invention relates to a densely integrated semiconductor apparatus formed by a SAC (Self-Aligned Contact) method and a manufacturing method therefor, and more particularly to a semiconductor apparatus, such as a DRAM, having fine MOS (Metal Oxide Semiconductor) transistors and a manufacturing method therefor.
The entire contents of Japanese Patent Application No. 8-158379 filed on Jun. 19, 1996 and Japanese Patent Application No. 9-158464 filed on Jun. 16, 1997 are incorporated herein by reference.
The degree of integration of a highly-integrated semiconductor apparatus represented by a DRAM (Dynamic Random Access Memory) having memory cells each of which is composed of one MOS transistor and one capacitor has been raised by reducing the minimum processing size. However, a variety of self-align technologies have been developed as technologies capable of forming fine devices without influence of an accuracy of aligning patterns in order to further raise the degree of integration. An example of the technologies above will now be described with reference to FIGS. 1A to 1D which is structured such that a contact hole for connecting a source/drain diffusion layer of a MOS transistor and a wiring layer of the same to each other is formed in a self-align manner with the gate electrode.
A gate insulator film 1, a gate electrode material 2, for example, poly crystal silicon, an oxide film 3 and an insulating film 4, such as a nitride film, are formed on a semiconductor substrate 100. Then, a lithography method and an anisotropic etching technique, such as RIE (Reactive Ion Etching) method, are employed to etch the insulating film 4, the oxide film 3 and the gate electrode material 2 so that a gate electrode is formed. Then, a sidewall oxide 3' is formed by, for example, thermal oxidation, and an ion implantation method is employed to add impurities, such as arsenic, to the substrate 100 so that a source/drain diffusion layer 8 is formed. FIG. 1A shows the cross section of a semiconductor apparatus in the foregoing state.
Then, an insulating film 6, such as a nitride film, is deposited to cover the formed gate electrode.
Then, an anisotropic etching technique, such as the RIE method, is employed to etch the insulating film 6 and the gate oxide film 1 to expose the substrate 100 and leave the insulating film 6 on the side surfaces of the gate electrode 2 and the insulating film 4. Then, an ion implantation method or the like is employed to add impurities, such as arsenic, to the substrate 100 so that a source/drain diffusion layer 9 is formed. FIG. 1C shows the cross section of a semiconductor apparatus in the foregoing state. The source/drain structure having a shape composed of the diffusion layers 8 and 9 is generally called as an "LDD structure" and formed for the purpose of improving the reliability of a transistor.
Moreover, an interlayer dielectric film 10 is deposited. Then, a resist film 11 is applied, and an opening is formed in the resist film 11 to include a contact hole region and overlapping the gate electrode 2. For example, an anisotropic technique, such as the RIE method, is employed to etch the interlayer dielectric film 10 to expose the substrate 100 in such a manner that the resist film 11 is used as a mask so that a contact hole 12 is formed. FIG. 1D shows the cross section of the semiconductor apparatus in the foregoing state.
Then, the resist film 11 is removed, a conductive material is deposited, and then a wiring layer to be connected to the diffusion layers 8 and 9 is formed.
When the contact hole 12 is formed, etching conditions are determined in such a manner that the speed, at which the interlayer dielectric film 10 is etched, is made to be higher than the speed, at which the insulating films 4 and 6 are etched. As a result, if the pattern of the contact hole 12 overlaps the gate electrode 2 as shown in FIG. 1D, etching of the insulating films 4 and 6 can be prevented. Therefore, a structure is realized in which the gate electrode 2 is covered with the insulating films 4 and 6. As a result, short circuit between the wiring layer (not shown) and the gate electrode 2 can be prevented. The foregoing technology capable of preventing short circuit between the wiring layer and the gate electrode 2 regardless of the pattern alignment accuracy between the pattern of the contact hole 12 and that of the gate electrode 2 is called a "self-align technology".
However, the contact hole 12 is, in a dense semiconductor apparatus, formed in a region between adjacent gate electrodes. Therefore, the recent trend of raising the density of the semiconductor apparatus results in the distance between the gate electrodes being shortened. As a result, there arises a problem in that the resistance of the contact portion is strengthened excessively because a satisfactorily large area cannot be provided for the contact hole.
A method for weakening the resistance of the contact portion is available in which the thickness of the side wall 6 is reduced. However, the conventional manufacturing method, in which ion implantation for forming the drain diffusion layer 9 is performed by using the side wall 6 as the mask, results in the drain diffusion layer 9 being deeply diffused to a position below the gate electrode 2 as shown in FIG. 2 if the thickness of the side wall 6 is reduced. As a result, the effective channel length L of the transistor is shortened unintentionally. Therefore, there arises a problem in that the operation of the transistor cannot easily be controlled.
As described above, when the contact hole is formed in the self-align manner with the gate electrode, a large area cannot be provided for the contact hole because of the trend of raising the density of the semiconductor apparatus. Thus, there arises a problem in that the resistance of the contact hole is strengthened excessively. If the thickness of the side wall is reduced in order to prevent strengthening of the resistance of the contact portion, the source/drain diffusion layer formed by using the side wall as the mask is deeply diffused in the direction of the gate length. As a result, there arises a problem in that the effective gate length is shortened and the controllability of the transistor deteriorates.